support floating point environment (fenv) on armhf (hard float) subarchs

patch by nsz. I've tested it on an armhf machine and it seems to be
working correctly.

arch/arm/bits/fenv.h

@@ -1,5 +1,18 @@
+#ifdef __SOFTFP__
 #define FE_ALL_EXCEPT 0
 #define FE_TONEAREST  0
+#else
+#define FE_INVALID    1
+#define FE_DIVBYZERO  2
+#define FE_OVERFLOW   4
+#define FE_UNDERFLOW  8
+#define FE_INEXACT    16
+#define FE_ALL_EXCEPT 31
+#define FE_TONEAREST  0
+#define FE_DOWNWARD   0x800000
+#define FE_UPWARD     0x400000
+#define FE_TOWARDZERO 0xc00000
+#endif
 
 typedef unsigned long fexcept_t;
 

src/fenv/armebhf/fenv.sub

@@ -0,0 +1 @@
+../armhf/fenv.s

src/fenv/armhf/fenv.s

@@ -0,0 +1,60 @@
+.global fegetround
+.type fegetround,%function
+fegetround:
+	mrc p10, 7, r0, cr1, cr0, 0
+	and r0, r0, #0xc00000
+	bx lr
+
+.global fesetround
+.type fesetround,%function
+fesetround:
+	mrc p10, 7, r3, cr1, cr0, 0
+	bic r3, r3, #0xc00000
+	orr r3, r3, r0
+	mcr p10, 7, r3, cr1, cr0, 0
+	mov r0, #0
+	bx lr
+
+.global fetestexcept
+.type fetestexcept,%function
+fetestexcept:
+	mrc p10, 7, r3, cr1, cr0, 0
+	and r0, r0, r3
+	bx lr
+
+.global feclearexcept
+.type feclearexcept,%function
+feclearexcept:
+	mrc p10, 7, r3, cr1, cr0, 0
+	bic r3, r3, r0
+	mcr p10, 7, r3, cr1, cr0, 0
+	mov r0, #0
+	bx lr
+
+.global feraiseexcept
+.type feraiseexcept,%function
+feraiseexcept:
+	mrc p10, 7, r3, cr1, cr0, 0
+	orr r3, r3, r0
+	mcr p10, 7, r3, cr1, cr0, 0
+	mov r0, #0
+	bx lr
+
+.global fegetenv
+.type fegetenv,%function
+fegetenv:
+	mrc p10, 7, r3, cr1, cr0, 0
+	str r3, [r0]
+	mov r0, #0
+	bx lr
+
+.global fesetenv
+.type fesetenv,%function
+fesetenv:
+	mrc p10, 7, r3, cr1, cr0, 0
+	cmn r0, #1
+	moveq r3, #0
+	ldrne r3, [r0]
+	mcr p10, 7, r3, cr1, cr0, 0
+	mov r0, #0
+	bx lr

src/fenv/armhf/fenv.sub

@@ -0,0 +1 @@
+fenv.s