add SPE FPU support to powerpc-sf

When the soft-float ABI for PowerPC was added in commit
5a92dd95c77cee81755f1a441ae0b71e3ae2bcdb, with Freescale cpus using
the alternative SPE FPU as the main use case, it was noted that we
could probably support hard float on them, but that it would involve
determining some difficult ABI constraints. This commit is the
completion of that work.

The Power-Arch-32 ABI supplement defines the ABI profiles, and indeed
ATR-SPE is built on ATR-SOFT-FLOAT. But setjmp/longjmp compatibility
are problematic for the same reason they're problematic on ARM, where
optional float-related parts of the register file are "call-saved if
present". This requires testing __hwcap, which is now done.

In keeping with the existing powerpc-sf subarch definition, which did
not have fenv, the fenv macros are not defined for SPE and the SPEFSCR
control register is left (and assumed to start in) the default mode.

arch/powerpc/bits/fenv.h

@@ -1,4 +1,4 @@
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 #define FE_ALL_EXCEPT 0
 #define FE_TONEAREST  0
 #else

arch/powerpc/reloc.h

@@ -1,4 +1,4 @@
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 #define FP_SUFFIX "-sf"
 #else
 #define FP_SUFFIX ""

configure

@@ -671,9 +671,7 @@ trycppif __mips_soft_float "$t" && SUBARCH=${SUBARCH}-sf
 fi
 
 if test "$ARCH" = "powerpc" ; then
-trycppif "__NO_FPRS__ && !_SOFT_FLOAT" "$t" && fail \
-  "$0: error: compiler's floating point configuration is unsupported"
-trycppif _SOFT_FLOAT "$t" && SUBARCH=${SUBARCH}-sf
+trycppif "_SOFT_FLOAT || __NO_FPRS__" "$t" && SUBARCH=${SUBARCH}-sf
 printf "checking whether compiler can use 'd' constraint in asm... "
 echo 'double f(double x) { __asm__ ("fabs %0, %1" : "=d"(x) : "d"(x)); return x; }' > "$tmpc"
 if $CC $CFLAGS_C99FSE $CPPFLAGS $CFLAGS -c -o /dev/null "$tmpc" >/dev/null 2>&1 ; then

src/fenv/powerpc/fenv-sf.c

@@ -1,3 +1,3 @@
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 #include "../fenv.c"
 #endif

src/fenv/powerpc/fenv.S

@@ -1,4 +1,4 @@
-#ifndef _SOFT_FLOAT
+#if !defined(_SOFT_FLOAT) && !defined(__NO_FPRS__)
 .global feclearexcept
 .type feclearexcept,@function
 feclearexcept:

src/math/powerpc/fabs.c

@@ -1,6 +1,6 @@
 #include <math.h>
 
-#if defined(_SOFT_FLOAT) || defined(BROKEN_PPC_D_ASM)
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__) || defined(BROKEN_PPC_D_ASM)
 
 #include "../fabs.c"
 

src/math/powerpc/fabsf.c

@@ -1,6 +1,6 @@
 #include <math.h>
 
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 
 #include "../fabsf.c"
 

src/math/powerpc/fma.c

@@ -1,6 +1,6 @@
 #include <math.h>
 
-#if defined(_SOFT_FLOAT) || defined(BROKEN_PPC_D_ASM)
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__) || defined(BROKEN_PPC_D_ASM)
 
 #include "../fma.c"
 

src/math/powerpc/fmaf.c

@@ -1,6 +1,6 @@
 #include <math.h>
 
-#ifdef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
 
 #include "../fmaf.c"
 

src/setjmp/powerpc/longjmp.S

@@ -37,7 +37,37 @@ longjmp:
 	lwz 29, 72(3)
 	lwz 30, 76(3)
 	lwz 31, 80(3)
-#ifndef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
+	mflr 0
+	bl 1f
+	.hidden __hwcap
+	.long __hwcap-.
+1:	mflr 4
+	lwz 5, 0(4)
+	add 4, 4, 5
+	andis. 4, 4, 0x80
+	beq 1f
+	.long 0x11c35b01 /* evldd 14,88(3) */
+	.long 0x11e36301 /* ... */
+	.long 0x12036b01
+	.long 0x12237301
+	.long 0x12437b01
+	.long 0x12638301
+	.long 0x12838b01
+	.long 0x12a39301
+	.long 0x12c39b01
+	.long 0x12e3a301
+	.long 0x1303ab01
+	.long 0x1323b301
+	.long 0x1343bb01
+	.long 0x1363c301
+	.long 0x1383cb01
+	.long 0x13a3d301
+	.long 0x13c3db01
+	.long 0x13e3e301 /* evldd 31,224(3) */
+	.long 0x11a3eb01 /* evldd 13,232(3) */
+1:	mtlr 0
+#else
 	lfd 14,88(3)
 	lfd 15,96(3)
 	lfd 16,104(3)

src/setjmp/powerpc/setjmp.S

@@ -37,7 +37,37 @@ setjmp:
 	stw 29, 72(3)
 	stw 30, 76(3)
 	stw 31, 80(3)
-#ifndef _SOFT_FLOAT
+#if defined(_SOFT_FLOAT) || defined(__NO_FPRS__)
+	mflr 0
+	bl 1f
+	.hidden __hwcap
+	.long __hwcap-.
+1:	mflr 4
+	lwz 5, 0(4)
+	add 4, 4, 5
+	andis. 4, 4, 0x80
+	beq 1f
+	.long 0x11c35b21 /* evstdd 14,88(3) */
+	.long 0x11e36321 /* ... */
+	.long 0x12036b21
+	.long 0x12237321
+	.long 0x12437b21
+	.long 0x12638321
+	.long 0x12838b21
+	.long 0x12a39321
+	.long 0x12c39b21
+	.long 0x12e3a321
+	.long 0x1303ab21
+	.long 0x1323b321
+	.long 0x1343bb21
+	.long 0x1363c321
+	.long 0x1383cb21
+	.long 0x13a3d321
+	.long 0x13c3db21
+	.long 0x13e3e321 /* evstdd 31,224(3) */
+	.long 0x11a3eb21 /* evstdd 13,232(3) */
+1:	mtlr 0
+#else
 	stfd 14,88(3)
 	stfd 15,96(3)
 	stfd 16,104(3)