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@@ -22,9 +22,8 @@ static inline int a_ctz_64(uint64_t x)
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return a_ctz_l(y);
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}
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-#if __ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__ \
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- || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ \
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- || __ARM_ARCH >= 7
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+#if ((__ARM_ARCH_6__ || __ARM_ARCH_6K__ || __ARM_ARCH_6ZK__) && !__thumb__) \
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+ || __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#if __ARM_ARCH_7A__ || __ARM_ARCH_7R__ || __ARM_ARCH >= 7
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#define MEM_BARRIER "dmb ish"
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@@ -39,6 +38,9 @@ static inline int __k_cas(int t, int s, volatile int *p)
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" " MEM_BARRIER "\n"
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"1: ldrex %0,%3\n"
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" subs %0,%0,%1\n"
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+#ifdef __thumb__
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+ " itt eq\n"
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+#endif
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" strexeq %0,%2,%3\n"
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" teqeq %0,#1\n"
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" beq 1b\n"
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