use register constraint instead of memory operand for riscv64 atomics

the "A" constraint is simply for an address expression that's a single
register, but it's not yet supported by clang, and has no advantage
here over just using a register operand for the address. the latter is
actually preferable in the a_cas_p case because it avoids aliasing an
lvalue onto the memory.

arch/riscv64/atomic_arch.h

@@ -9,13 +9,13 @@ static inline int a_cas(volatile int *p, int t, int s)
 {
 	int old, tmp;
 	__asm__ __volatile__ (
-		"\n1:	lr.w.aqrl %0, %2\n"
+		"\n1:	lr.w.aqrl %0, (%2)\n"
 		"	bne %0, %3, 1f\n"
-		"	sc.w.aqrl %1, %4, %2\n"
+		"	sc.w.aqrl %1, %4, (%2)\n"
 		"	bnez %1, 1b\n"
 		"1:"
-		: "=&r"(old), "=r"(tmp), "+A"(*p)
-		: "r"(t), "r"(s)
+		: "=&r"(old), "=r"(tmp)
+		: "r"(p), "r"(t), "r"(s)
 		: "memory");
 	return old;
 }
@@ -26,13 +26,13 @@ static inline void *a_cas_p(volatile void *p, void *t, void *s)
 	void *old;
 	int tmp;
 	__asm__ __volatile__ (
-		"\n1:	lr.d.aqrl %0, %2\n"
+		"\n1:	lr.d.aqrl %0, (%2)\n"
 		"	bne %0, %3, 1f\n"
-		"	sc.d.aqrl %1, %4, %2\n"
+		"	sc.d.aqrl %1, %4, (%2)\n"
 		"	bnez %1, 1b\n"
 		"1:"
-		: "=&r"(old), "=r"(tmp), "+A"(*(long *)p)
-		: "r"(t), "r"(s)
+		: "=&r"(old), "=r"(tmp)
+		: "r"(p), "r"(t), "r"(s)
 		: "memory");
 	return old;
 }