hongwenjun/musl

miroir de https://git.musl-libc.org/git/musl

Auteur	SHA1 Message	Date
Luís Marques	83350eb17b fix riscv64 a_cas inline asm operand sign extension	il y a 4 ans
Palmer Dabbelt	7d5c5706a0 correct the operand specifiers in the riscv64 CAS routines	il y a 5 ans
Rich Felker	f0eb2e77b2 use register constraint instead of memory operand for riscv64 atomics	il y a 5 ans
Rich Felker	2dcbeabd91 fix riscv64 atomic asm constraints	il y a 5 ans
Rich Felker	0a48860c27 add riscv64 architecture support	il y a 5 ans